1. Field of the Invention
The present invention relates to a display device including a thin film transistor (TFT) array substrate.
2. Discussion of the Related Art
Recently, as the times advance to the information-oriented society, flat panel display devices are needed because having good characteristics in thinning and lightening thereof and the realization of low consumption power. In the flat panel display devices, liquid crystal display (LCD) devices are good in resolution, color display, and image quality, and thus are commercialized as display devices for notebook computers, tablet computers, and desktop computers.
Generally, LCD devices are devices in which two substrates with electrodes formed therein are disposed such that the electrodes of the two substrates face each other, liquid crystal is injected between the facing electrodes, liquid crystal molecules are realigned with electric fields that are generated by applying different voltages to the facing electrodes, and thus, an image is realized by a light transmittance that is changed according to the realignment of the liquid crystal molecules.
The LCD devices include a liquid crystal display panel in which a liquid crystal layer is formed between two substrates, a backlight that irradiates light on the liquid crystal display panel, and a driving circuit part for driving the liquid crystal display panel.
Generally, the driving circuit part is implemented on a printed circuit board (PCB). The driving circuit part includes: a gate driving circuit part that is connected to gate lines of the liquid crystal display panel and applies a gate signal to the gate lines; and a data driving circuit part that is connected to data lines of the liquid crystal display panel and applies data signals to the respective data lines.
The driving circuit part is mounted on a tape carrier package (TCP) or a chip on film (COF), and attached to one side or both sides of the liquid crystal display panel.
Recently, gate-in panel (GIP) type LCD devices in which some circuits of a gate driving circuit part are formed simultaneously with a process of forming TFTs of a liquid crystal display panel are proposed for reducing the volume and weight of the LCD device affected by a driving circuit part and decreasing a bezel width.
FIG. 1 is a plan view schematically illustrating a related art GIP type LCD device.
Referring to FIG. 1, the related art GIP type LCD device includes a first substrate 10 that is a lower substrate, a second substrate 20 that is an upper substrate, and a seal pattern 30 in which the first and second substrates 10 and 20 are facing-coupled to each other with a liquid crystal layer (formed between the first and second substrates 10 and 20, not shown) therebetween.
The first substrate 10 is a TFT array substrate, and includes a display area DA for displaying an image and a non-display area NDA that is formed to surround the display area DA and cannot display an image.
A plurality of gate lines 11, a plurality of data lines 12, a plurality of thin film transistors T, and a plurality of pixel electrodes PE are formed in the display area DA of the first substrate 10.
The gate lines 11 and the data lines 12 intersect to define a plurality of pixel areas. Each of the thin film transistors T is a switching element, and is connected to a corresponding gate line 11 and a corresponding data line 12 and turned on with a gate signal applied to the gate line 11 to supply a data signal, applied from the data line 12, to a corresponding pixel electrode PE.
Each of the pixel electrodes PE is connected to a corresponding thin film transistor T, and generates an electric field with a data signal supplied from the thin film transistor T to realign the liquid crystal molecules of the liquid crystal layer.
A pad part 13, a plurality of data link lines 14, a common voltage line part 15, a gate link part 16, and a built-in shift register 17 are disposed in the non-display area NDA of the first substrate 10.
The pad part 13 includes a data pad part 13a, a gate pad part 13b, and a common voltage pad part 13c. 
The data pad part 13a is disposed at an upper side of the non-display area NDA which is one side surface (upper side of a first gate line) of an upper side of the first substrate 10, and connected to an external driving circuit part (not shown). The gate pad part 13b is disposed at one side of the data pad part 13a, and connected to the external driving circuit part. The common voltage pad part 13c is disposed at one side of the gate pad part 13b, and connected to a common voltage generator (not shown) of the external driving circuit part.
Each of the data link lines 14 is extended from a corresponding data line 12, and connects a corresponding data pad of the data pad part 13 and the data line 12.
The common voltage line part 15 includes a plurality of common voltage link lines that are formed inside the seal pattern 30 at certain intervals. One side end of each of the common voltage lines is electrically connected to the common voltage pad part 13c through one common voltage extension line 15a. Furthermore, a common voltage connection line (not shown) is electrically connected to a common electrode (not shown) which is formed in a corresponding pixel area.
The gate link part 16 includes a gate start signal line, a plurality of clock signal lines, a forward signal line, a backward signal line, a reset signal line, and a ground voltage line which are formed at certain intervals between the common voltage line part 15 and the built-in shift register 17. Each of the signal lines of the gate link part 16 is electrically connected to the gate pad part 13b of the pad part 13 through a gate link line 16a. Each signal line of the gate link part 16 is selectively connected to the built-in shift register 17 through a gate control signal connection line 16b. 
The built-in shift register 17 is formed in the non-display area NDA of the first substrate 10 simultaneously with the above-described process of forming the thin film transistors T. The built-in shift register 17 generates the gate signal with a gate start signal, a plurality of clock signals, a forward signal, a backward signal, a reset signal, and a ground voltage which are supplied from the gate link part 16, and supplies the gate signal to the gate lines 11. To this end, the built-in shift register 17 includes a plurality of stages 17s respectively connected to the gate lines 11.
Each of the stages 17s supplies a clock signal, supplied through one of the clock signal lines, as the gate signal to a corresponding gate line 11 in response to the gate start signal which is supplied from the gate start signal line or a previous stage. The stages 17s sequentially operate according to the gate start signal which is supplied from the gate start signal line or a previous stage, and thus sequentially supply the gate signal from the first gate line to the last gate line or sequentially supply the gate signal from the last gate line to the first gate line.
The second substrate 20 includes a black matrix (not shown) that is defined in each pixel area of the first substrate 10, and a color filter layer (not shown) that is formed to overlap each pixel area of the first substrate 10. The second substrate 20 has a size corresponding to the size of the first substrate 10 except the size of the pad part 13 of the first substrate 10.
The seal pattern 30 is formed along the non-display area NDA of the first substrate 10 to overlap an edge portion of the second substrate 20, and facing-couples the first and second substrates 10 and 20 with the liquid crystal layer therebetween. In this case, the seal pattern 30 overlaps the edge portion of the second substrate 20, and is formed at an outer portion of the common voltage line part 15 left and right with respect to the LCD device and formed at an outer portion of the display area DA upward and downward with respect to the LCD device.
In the related art GIP type LCD device, since the seal pattern 30 and the non-display area of the first substrate 10 cannot display an image, the seal pattern 30 and the non-display area of the first substrate 10 are covered by a case (not shown). Here, a portion covered by the case is called a bezel.
For this reason, in the related art GIP type LCD device, a bezel width is increased by the built-in shift register 17 and the seal pattern 30 which are disposed in the non-display area of the first substrate 10. Also, in the related art GIP type LCD device, since a scribing line overlaps the seal pattern 30 in a scribing process of cutting the coupled first and second substrates 10 and 20, it is not easy to perform the scribing process, and, a crack occurs in the first and second substrates 10 and 20 due to the reduced width of the seal pattern 30 and a portion of the seal pattern 30 which is cut by the scribing process, causing the decrease in rigidity of the first and second substrates 10 and 20.